The present invention relates to an improved technique for testing and measuring electronic multilayer laminates to determine if the layers thereof are properly registered.
Multilayer circuit boards and other multilayer electronic devices are manufactured by preparing individual layers and joining them together typically with lamination using heat and pressure. Typically, these laminate layers are composed of a dielectric material which is provided one or both surfaces thereof having a metallized coating defining an electrical circuitry pattern. In manufacture, the layers are brought together in juxtaposed relation so that the layers are aligned with one another. Desirably, the layers remain in registration after the lamination process so that a multilayer product is produced with the different layers in desired registered relation.
In manufacture of multilayer circuit boards or cards, multichip modules and chip carriers and the like, it is not uncommon for the respective laminate layers, or portions thereof, to become out of registration during the lamination process. This is due to a number of reasons including stresses in the assembly due to temperature and pressure, relative motion of the different layers during the lamination process, changes in shape of the laminate layers as a result of curing, and so forth.
Because of this phenomenon, it is not uncommon in industry for electronic multilayer structures, after they are made, to be tested to determine if the individual layers thereof are in proper registration. Normally, this is done by including, an X-ray dot (i.e., a dot of a material responsive to X-ray radiation) at a specified and known geometric location in the layers to be tested and then irradiating the laminate with X-ray radiation. The pattern of X-ray radiation passing out of the laminate is then read to determine if the two dots, and hence the layers containing the dots, are in registration. The measurement of the actual distance between the features provides information on the total overall positional differences between conductors and other features located on each interconnection layer of the structure.
As the patterns of electrical circuitry formed in electronic multilayer laminates become more and more complex, the size and spacing of the circuit lines in these patterns becomes smaller and smaller. Also, the spacing of the interlevel connections decreases. Concomitantly, the displacement between layers necessary to make a laminate defective becomes less and less. Unfortunately, the above-described X-ray dot technique is becoming inadequate to measure these small displacements, since its sensitivity is inherently limited. For example, future designs will require measurement sensitivities on the order of 50 ppm or less for small boards, e.g. 10.times.10 inches or less, which is not possible using X-ray dot technology alone.
In addition, due to the increased complexity of the individual layers and therefore their cost, it is also important to have a method to determine the layer to layer alignment prior to joining the levels together.
Accordingly, there is a need for a new process for testing multilayer circuit boards or cards, multichip modules and chip carriers and other electronic multilayer laminates for layer registration which is simple and easy to carry out and is also far more sensitive than techniques available at the present time.